Van der Waals Ferroelectric CuCrP2S6-Enabled Hysteresis-Free Negative Capacitance Field-Effect Transistors
Han Chen, Yinfeng Long, Shiyu Zhang, Kai Liu, Mingfeng Chen, Jinxiu Zhao, Mengwei Si, and Lin Wang
Abstract
The relentless pursuit of miniaturization and reduced power consumption in information technology demands innovative device architectures. Negative capacitance field‐effect transistors (NC‐FETs) offer a promising solution by harnessing the negative capacitance effect of ferroelectric materials to amplify gate voltage and achieve steep subthreshold swings (SS). In this work, 2D van der Waals (vdW) ferroelectric CuCrP2S6(CCPS) is employed as the gate dielectric to realize hysteresis‐free NC‐FETs technology. Scanning microwave impedance microscopy (sMIM) is employed to investigate the dielectric property of CCPS, revealing a thickness‐independent dielectric constant of ≈35. Subsequently, NC‐FETs are fabricated with MoS2channel, and the capacitance matching conditions are meticulously investigated. The optimized devices exhibit simultaneously ultra‐steep SS (≈12 mV dec⁻¹) and negligible hysteresis, with immunity to both voltage scan range and scan rate. Finally, a resistor‐loaded inverter is demonstrated manifesting a low operation voltage down to 0.2 V and hysteresis‐free transfer characteristics. This work paves the way for the development of high‐performance, low‐power electronics by exploiting 2D vdW ferroelectric materials.
Summary of the paper
This study utilizes 2D van der Waals (vdW) ferroelectric CuCrP2S6(CCPS) as the gate dielectric to develop hysteresis-free negative capacitance field-effect transistors (NC-FETs) for low-power electronics.
Key findings include:
Scanning Microwave Impedance Microscopy (sMIM) characterizes CCPS’s dielectric properties, revealing a thickness-independent dielectric constant (~35) across 6–70 nm, validated by finite element analysis (FEA) and capacitance-voltage (C-V) measurements.
Optimized NC-FETs with MoS2channels (via precise capacitance matching between CCPS and MoS2) exhibit ultra-steep subthreshold swing (~12 mV/dec), negligible hysteresis (insensitive to voltage scan range/rate), and high on-off ratio (~10⁶).
A resistor-loaded inverter based on the NC-FET operates at a low supply voltage (0.2 V) with ultralow power consumption (1.67 pW) and maintains a voltage gain >1, meeting low-power logic circuit requirements.
This work highlights CCPS' s potential for advancing high-performance, low-power post-Moore NC-FET technologies.
In this article, the specific application scenarios and functions of scanning microwave impedance microscopy SMIM are as follows:
- Characterizing the dielectric properties of CCPS: Using sMIM technology combined with finite element simulation (FEA), the relative dielectric constant of van der Waals ferroelectric material CuCrP₂S₆ (CCPS) was quantitatively measured and found to be thickness-independent in the thickness range of 6-70 nm, with a value stable at ≈35. This result is consistent with the capacitance-voltage (C-V) measurement, providing key parameters for subsequent device capacitance matching design.
- Obtain CCPS thickness-signal relationship: Extract the signal contrast between CCPS nanosheets and Au substrate through sMIM imaging, and observe a quasi-inverse relationship between signal and thickness, which further assists the quantitative analysis of dielectric constant and clarifies the thickness adaptation range of CCPS as a gate dielectric material.
- Support NC-FET device design: Based on the dielectric constant of CCPS (≈35) measured by sMIM, combined with the dielectric constant of MoS₂ (≈7), the thickness matching conditions of CCPS and MoS₂ are derived (T_CCPS ≤ (T_MoS₂・ε_CCPS)/ε_MoS₂), in order to optimize the NC-FET device structure, achieve hysteresis-free characteristics and ultra-steep sub-threshold swing (≈12 mV/dec) provides data support.
